For today's transistor fabrication, the surface of the semiconductor substrate has to be extremely smooth. This is because any roughness on the semiconductor substrate is a source for surface roughness scattering that degrades carrier mobility during operation of a metal-oxide-semiconductor field-effect-transistor (MOSFET). In silicon (Si) MOSFET production industry, the requirement for an electronic device-grade Si surface is a surface roughness of 2 Å. For silicon, this is mainly achieved by chemical mechanical polishing (CMP) prior to any fabrication. In addition, to mitigate surface/sidewall roughness caused by etching, ion implantation, and other processes, a thin thermal oxide is intentionally grown and removed.
Germanium (Ge) is a candidate material for next generation devices (MOSFETs) because it has higher carrier mobility than Si and is compatible with traditional Si Complementary Metal-Oxide-Semiconductor (CMOS) processes. However, epitaxially grown Ge (epi-Ge) on Si typically has a root-mean-square (rms) roughness of about 7 Å because of a 4% lattice mismatch. Even with bulk Ge, the surface cannot recover to its original roughness following extra-heavy ion implantation during which void-like structures form on the surface that cannot be recovered with thermal annealing. This needs to be reduced before forming Ge-based MOSFET devices. Although surface roughness can be reduced via CMP, it is tricky to do so during device processing without risking damage to other elements in the device.